- Marvell Structera X 2404 enables DDR4 reuse without purchasing new DRAM
- Twelve DIMMs per controller deliver 1.5TB physical memory capacity
- Memory compression effectively doubles usable capacity using LZ4 at line rate
Hyperscalers under pressure from rising memory prices could turn to decommissioned DDR4 modules as a practical resource.
Marvell Structera X 2404 is a CXL-based memory expander designed to make large-scale DDR4 module reuse feasible.
When operators install 128GB drives taken from retired systems, the controller offers up to 1.5TB of physical capacity without the need for new DRAM.
Structera X 2404 Implementation Design
The Structera
It supports four DDR4 channels and allows three DIMMs per channel, creating a total of twelve modules connected to a single controller.
This approach appeals to hyperscalers due to the large amounts of older modules stored from previous upgrade cycles.
It also reduces manufacturing needs because only the controller, board, and cable require production, not the DRAM itself.
The DDR4 model focuses on cost, but some operators need more performance than older modules can offer.
The Structera X 2504 is suitable for these environments and uses DDR5 RAM in four channels.
It connects via CXL 2.0 over PCIe Gen5 and offers more bandwidth because it bypasses the CPU memory channels.
This design is attractive for implementations that require faster performance while also seeking expansion beyond the limits of the processor’s DDR5 DIMM slots.
The most notable capability of both devices is memory compression, which changes how capacity is delivered and priced.
Marvell uses LZ4 at line speed and reports ratios between 1.8x and 2x during normal operation. This means that a 1.5TB capacity can be expanded up to 3TB.
This approach allows hyperscalers to treat repurposed DDR4 as a larger, cheaper pool than its physical size suggests.
It also reduces pressure on DDR5 supply chains because systems can rely on compressed expansion rather than purchasing additional modules.
That said, latency remains the main concern because independent testing under real workloads has not yet been done.
CXL already introduces additional delay and compression adds more uncertainty when memory access becomes unpredictable.
Without third-party random read latency testing, it is unclear whether these devices perform well in sparse access patterns.
Random reads plague many production systems, and slow responses can negate the benefits of additional capacity.
This uncertainty represents the greatest technical risk because latency determines whether the expansion behaves like real memory or a slower level.
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