- SPHBM4 dramatically reduces pin count while preserving hyperscale-class bandwidth performance
- Organic substrates reduce packaging costs and relax route restrictions in HBM designs
- Serialization moves complexity to the base logic and signaling silicon layers
High-bandwidth memory has evolved around extremely wide parallel interfaces, and that design choice has defined both performance and cost limitations.
HBM3 uses 1024 pins, a figure that already exceeds the limits of dense silicon interposers and advanced packaging.
The JEDEC Solid State Technology Association is developing an alternative known as Standard High Bandwidth Memory Package 4 (SPHBM4), which reduces physical interface width while preserving overall performance.
The HBM4 interface duplicates the HBM3
The HBM4 standard specification doubles the width of the HBM3 interface to 2048 pins, with digital signals passing through each contact to increase aggregate performance.
This scaling approach improves bandwidth, but also increases routing complexity, substrate demands, and manufacturing overhead, worrying system designers.
The planned SPHBM4 device uses 512 pins and relies on 4:1 serialization while operating at a higher signaling frequency.
In terms of bandwidth, one SPHBM4 pin is expected to support the equivalent workload of four HBM4 pins.
This approach shifts the complexity from pin counting to signaling technology and base logic design.
Reducing the number of pins allows for wider spacing between contacts, which directly affects packaging options.
JEDEC claims that this relaxed step allows connection to organic substrates instead of silicon interposers.
Silicon substrates support very high interconnect densities with pitches greater than 10 micrometers, while organic substrates typically operate closer to 20 micrometers and cost less to manufacture.
Therefore, the interposer that connects the memory stack, its base logic die, and an accelerator would move from a silicon-based design to an organic substrate design.
The HBM4 and SPHBM4 devices are expected to offer the same memory capacity per stack, at least at the specification level.
However, the organic substrate assembly allows for longer channel lengths between the accelerator and the memory stacks.
This configuration may allow for more SPHBM4 stacks per package, which could increase total memory capacity compared to conventional HBM4 designs.
Achieving this result requires a redesigned base logic matrix, as the SPHBM4 memory stacks involve a reduction in the number of pins from four to one relative to HBM4.
HBM is not general purpose memory and is not intended for consumer systems.
Its use cases remain focused on AI accelerators, high-performance computing, and GPUs in data centers operated by hyperscalers.
These buyers work at scales where memory bandwidth directly impacts revenue efficiency, justifying continued investment in expensive memory technologies.
SPHBM4 does not alter this usage model, preserving HBM-class bandwidth and capacity while optimizing system-level cost structures that are important primarily for hyperscale deployments.
Despite references to lower cost, SPHBM4 does not indicate a path to consumer RAM markets.
Even with organic substrates, SPHBM4 remains a stacked memory with a specialized logic base and tight coupling to accelerators.
These features do not align with consumer DIMM-based memory architectures, pricing expectations, or motherboard designs.
Any cost reductions apply within HBM’s own ecosystem and not across the broader memory market.
However, for SPHBM4 to become a viable standard, support from major vendors is required.
“JEDEC members are actively shaping the standards that will define next-generation modules for use in AI data centers…” said Mian Quddus, Chairman of the JEDEC Board of Directors.
Major vendors, including Micron, Samsung and SK Hynix, are members of JEDEC and are already developing HBM4E technologies.
“Our #NuLink D2D/D2M interconnect solution has demonstrated the ability to achieve 4 TB/s of bandwidth in a standard package, which is up to twice the bandwidth required by… the HBM4 standard, so we hope to build on the work JEDEC has done with SPHBM4…” said Eliyan, a basic logic die semiconductor company.
Through Blocks and files
Follow TechRadar on Google News and add us as a preferred source to receive news, reviews and opinions from our experts in your feeds. Be sure to click the Follow button!
And of course you can also follow TechRadar on TikTok for news, reviews, unboxings in video form and receive regular updates from us on WhatsApp also.
