- IBM pushes transistor density below the dreaded nanometer barrier
- NanoStack abandons flat chip designs in favor of vertical transistor stacking
- The prototype offered 50% more performance during the IBM laboratory testing phases
IBM has unveiled what it describes as the world’s first sub-1nm chip technology, packing nearly 100 billion transistors on a surface the size of a fingernail.
The advancement revolves around a new 3D NanoStack architecture that brings transistor scaling to the 0.7 nm or 7 angstrom era.
For context, today’s most advanced commercial chips typically sit around the 2nm mark, which is a substantial jump in density.
Build up to keep Moore’s Law alive
The semiconductor industry has spent decades squeezing more transistors into smaller and smaller pieces of silicon to improve computing performance.
That process has become increasingly difficult as transistor dimensions approach the scale of just a few atoms in modern processors.
IBM’s approach avoids further horizontal compression by stacking transistor layers vertically through a three-dimensional nanosheet architecture.
The design includes nearly twice the transistor density of IBM’s 2nm chip technology introduced in 2021.
According to the company, the architecture also offers approximately 40% more SRAM scaling to support increasingly demanding AI workloads.
This vertical approach allows engineers to separate n-type and p-type transistors into distinct layers, which IBM says allows for independent optimization of materials for each.
He compared it to building a large block of flats instead of houses in a city.
“IBM’s NanoStack is like proposing a 100-story skyscraper,” said Professor Alan Woodward, a computer scientist at the University of Surrey.
Using this analogy, IBM’s closest competitors, such as Intel and Samsung, are 30- to 50-story buildings, a long way from IBM.
In testing, the company reported a 50% performance improvement and 70% greater power efficiency compared to its existing 2nm chips, along with a 40% gain in on-chip memory scaling.
Despite the performance improvements cited, the technology is still years away from commercial use, and IBM estimates that production could begin within five years at the earliest.
“With our new NanoStack architecture, we are not only making transistors smaller, we are reinventing the way chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, IBM research director and IBM Fellow.
The trade-offs behind increased density
Vertical stacking introduces complications primarily around heat dissipation, as transistors generate heat that becomes more difficult to handle when layered closely together.
This same tight spacing also increases risks for wafer alignment, as layers must be joined together with extreme precision to avoid malfunctions.
The researchers recognize that when the spaces between layers become too thin, transistors may not turn off properly, undermining the density gains that NanoStack is meant to offer.
These engineering tradeoffs are symptoms of a deeper problem facing the entire chip industry.
For decades, manufacturers have relied on Moore’s Law, according to which the transistor count pattern doubles approximately every two years.
But that pace has become harder to maintain as designs approach the physical limits of individual atoms.
Whether NanoStack actually extends that trajectory another decade, as IBM projects, depends on whether these unsolved manufacturing challenges can be solved at scale.
It is partly for this reason that IBM has attracted partners such as ASML, Lam Research and Tokyo Electron, indicating an industry-wide effort behind this push towards angstrom-level scaling.
Still, similar bold claims accompanied IBM’s 2nm chip unveiling in 2021, but translating lab success into mass production historically takes longer than initial announcements.
Via IBM
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