- Mi400 APU de AMD lands in 2026, increasing AI, HPC and calculation efficiency
- The new design presents two aid with eight XCD, doubling the density of the MI300
- Multimedia io die offloads io tasks and can integrate xilinx fpga tech
AMD’s APU MI400 APU will arrive in 2026, designed for AI work loads, automatic learning and HPC, the MI400 will be based on modular architecture based on Chiplet of Team Red and the computing density, energy efficiency, is expected to increase and scalability.
You can also play a role in future supercomputing projects, including a possible successor of El Capitan, but so far, AMD has only confirmed that the MI400 will use the “Next” architecture of ADNC.
However, ut a patch that updates the API header for month (microengine scheduler) V12, seen by Coelacanth’s dream (and reported by Videocardz), provides information about its Chipplet configuration.
According to the patch, the MI400 will feature two active inter -positive trochers (AIDS), each with four accelerated grades (XCD), for a total of eight XCD. This doubles the XCD count for help compared to the MI300. By integrating more calculation calculations in less interposers, AMD could reduce latency and improve efficiency while increasing data performance, which is essential for AI and HPC workloads.
However, like Coelacanth’s dream He points out: “If the MI400 follows a similar CPU complex die (CCD) and the help partition such as the MI300, where some AIDS are dedicated to the CPU instead of accelerators, then the maximum number of XCD in some configurations could be limited to four, potentially reducing the XCD count compared to the APU MI300A “.
An intriguing addition to MI400 is the multimedia IO (medium) dice, which separates the AIDS multimedia engine. The MID will probably manage memory controllers, media engines and interface logic, allowing computation trochers to focus on processing tasks. The patches suggest support for up to two media, probably assigning one for help.
This new component could be the first AMD integration of Versal/Xilinx FPGA technology in its accelerator line. AMD announced in 2022 that it planned to incorporate the AI inference engine with FPGA with Xilinx FPGA in its CPU portfolio. It could also be an acceleration card of the Alveo series data center.
The patches also refer to a registration reallocation table (RRMT), allowing firmware to direct registration transactions to specific aid, XCD or MIDS.
AMD has not yet launched any official renders or specifications for the MI400 series, but with the accelerator that is expected to be launched in 2026, after the arrival of the Instinct Mi350 series (built in the Anc 4) architecture at the end of this Year, luckily more details will emerge. soon.
