- The Cadence tool helps the energy demands of the GPU of the NVIDIA model in billions of cycles
- Early analysis will help Nvidia improve the efficiency of chips and energy consumption levels
- NVIDIA and AMD hardware contribute to cadence emulation and the prototype creation platform
Cadence Design Systems has created a dynamic power analysis tool designed to handle very large chip designs, including Nvidia Rubin GPU that entails more than 40 billion doors.
Eenews Europe Reports The software operates in the Palladium Z3 emulator, which allows engineers to examine with incredibly high precision how energy is consumed in billions of cycles in just a few hours.
This is especially useful for AI accelerators such as Rubin, where workloads vary widely and can emphasize different design areas at different times.
Go to Early Bottlenecks
Power modeling is increasingly important as chips grow and increase energy demands.
Rubin could draw around 700W for a single dice, with multiple chip settings that consume up to 3.6kw. When executing early simulations, design equipment can dimension the networks with greater precision, detect and address bottlenecks before the chip reaches production.
Eenews He says it has been reported that Rubin requires a respite. It was recorded with TSMC in June in its 3NM N3P process, but Nvidia is looking to increase the performance in preparation for a battle against the next AMD MI450.
This could delay Rubin’s first samples in 2026, although shipments are expected to begin at the end of that year.
The Cadence DPA application will play a central role in the navigation of these challenges, Eenews says. According to reports, the emulator can handle up to 48 billion doors, which supports the estimate of the chip levels and averages in the raffle.
This allows developers to balance performance efficiently while limiting the delay risks of low or large networks.
The Palladium Z3 platform itself uses the Bluefield Data Processing Unit of NVIDIA and the quantum networks of Infinib and networks to connect with the Prototype System X3 FPGA.
The protium platform is based on FPGA AMD Ultrascale, which can run RTL models of designs, allowing the first software tests before Silicon is available. In this way, both Nvidia and AMD Hardware are involved in Rubin’s design cycle support.
Cadence first introduced a DPA application in 2016, but the growing complexity of AI processors has made such tools essential.
In the case of Rubin, the prototype analysis and creation platforms will help engineers to administer energy demands on a scale that is not seen before, and the lessons learned here are expected to be filtered into consumer products as maturity technology.
