- Sandisk says that 3D matrix memory will be an affordable replacement for dram
- Will deliver a dram type yield 4 times the capacity and half of the cost
- Sandisk says it will become more affordable as technology matures
In its recent Sandisk 2.0 investor day session, the Flash storage giant released a series of new SSD, which includes a 128TB data center model, while describing its ambitious roadmap for units still Larger: a SSD of 256 TB in 2026, a 512TB SSD in 2027, and a huge campaign of 1 percent is expected a few years later.
Sandisk is eager to calm any investor staggering after its separation from Western Digital, and beyond discussing its strategy to increase returns and margins, the company also removed its innovative 3D matrix memory, a scalable memory technology that, According to reports, it promises a dram performance four times the capacity and half of the cost.
Sandisk has positioned the memory of the 3D matrix as an affordable solution in response at the end of Moore’s Law for DRAM, where the stagnation scale, an extensive computing memory gap and high memory costs have become important challenges . The company says that its scalable memory architecture will break the “memory wall”, solving the problem of memory capacity and bandwidth that struggles to maintain the rhythm of the increasing processing demands.
More profitable
Developed in collaboration with IMEC, Sandisk’s 3D matrix memory is based on a dense matrix architecture with a new memory cell design while compatibility with open industry standards is maintained, such as CXL.
The company states that its new memory technology will be increasingly profitable over time. According to a shared sandisk chart, by the year 6, the 3D matrix memory will achieve more than 50% cost savings per bit compared to DRAM, with a significantly more pronounced decrease in $/GB, which makes it a Alternative more affordable to traditional DRAM solutions.
The company’s development map, which is shown below, describes a series of milestones, with the transition from a 150 mm WD FAB to an IMEC installation of 300 mm in 2024, marking the first significant step of The technology towards large -scale production.
As of 2017, the project has evolved from isolated devices to passive matrices, CMOS development vehicles. Gen1 media samples will be the next big step and they are expected to reach capabilities of 32-64 GBIT, although there are still no details about gross performance.
