- WeeBit ReRAM memory fits on chips without changing existing transistor structures
- Each ReRAM cell stores data using resistive switching, not traditional flash methods.
- ReRAM can handle between 100,000 and 1 million write cycles
Texas Instruments’ decision to license Weebit Nano’s embedded ReRAM has revived claims that flash memory has reached structural limits.
The deal follows previous agreements with SkyWater, DB HiTek and Onsemi, marking a steady escalation of manufacturing partners rather than an abrupt endorsement.
Weebit CEO Coby Hanoch said All about circuits that the progression was deliberate, and that each stage increased both the scale of the process and the credibility of the industry.
Architecture and manufacturing friction options.
“Every time we go up an order of magnitude,” he said. “From SkyWater to DB HiTek, to Onsemi and now to TI. We are now in the big league.”
Weebit implements its ReRAM as an end-of-line module, allowing integration without altering the front-end transistor structures.
This approach keeps additional wafer costs close to 5%, compared to the much higher overheads associated with integrated flash processes.
The memory cell itself is based on resistive switching rather than floating gate storage, allowing bit-level access without block erase operations.
These design decisions are framed as pragmatic rather than revolutionary, and are based on standard materials and conventional manufacturing tools.
“We said from day one that we would use standard materials, standard tools and standard flows,” he said. “We didn’t want to give excuses to factories not to work with us.”
From a specs standpoint, Weebit reports write speeds up to 100 times faster than built-in flash, along with endurance ranging from 100,000 to 1 million cycles.
The company reports lower power consumption due to reduced operating voltages and pass-through modes.
Its CEO states bluntly that “power, speed, endurance, temperature and cost, on all the axes important to embedded memory, ReRAM looks better than flash.”
The company also emphasizes immunity to electromagnetic interference, contrasting its technology with MRAM.
“We have seen cases where magnetic fields corrupted MRAM in consumer environments,” Hanoch said, adding that large manufacturers considered that risk unacceptable.
As process nodes shrink below 28nm, integrated flash becomes increasingly difficult to reliably scale.
Designers often compensate by pairing logic arrays with external flash and storing data in SRAM at boot, which increases complexity and power consumption.
Hanoch maintains that non-volatile ReRAM eliminates this inefficiency, allowing for instant boot and tighter security limits.
The higher density of ReRAM compared to SRAM allows peripheral devices to store more data on the chip, which directly improves calculation accuracy.
“More bits on the same silicon means higher accuracy for inference,” he said, while pointing to demonstrated neuromorphic experiments in which “the ReRAM bit behaves like a synapse.”
Weebit cites industry forecasts that project ReRAM revenue will grow around 45% per year, potentially reaching $1.7 billion within six years.
But its revenue remains modest, though growing, and the company attributes slower adoption to institutional caution rather than technical shortcomings.
“The biggest barrier is human nature,” Hanoch said, despite pointing to silicon’s multi-node work and qualifications for mass production.
It remains to be seen if TI’s endorsement confirms that “ReRAM is the replacement for flash memory.”
Still, the search for universal memory remains unresolved, with alternatives such as ULTRARAM, developed by Quinas Technology, entering the field last year.
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