- Apollo 2 switch admits Gen 6.2 and Cxl 3.1 inside a single hybrid chip
- Xconn wants to redefine bandwidth limits, but real world results remain completely not tested
- Intel and Xconn are collaborating to prove the compatibility of the full pile in PCIE -based ecosystems
Xconn Technologies is preparing to demonstrate what it describes as a PCIE Gen 6.2 and CXL 3.1 solution completely integrated from end to end in the next future event of memory and storage (FMS25).
The company is positioning the launch as a critical step to meet the performance needs of the workloads of AI and Data Center.
However, as with any demonstration of initial stage technology, the scalability and reliability of the real world are still open questions.
Hybrid switch with theoretical flexibility
The company Apollo 2 of the company will be the core of this presentation, marketed as the first hybrid switch of the industry to admit both PCIE Gen 6.2 and CXL 3.1 Within a single chip, it is said that simplifies interconnection designs and improves scalability.
“Xconn is excited to take the PCIE Gen 6.2 and CXL 3.1 switches, with available samples,” said Gerry Fan, CEO of Xconn Technologies.
“As the industry accelerates towards more -centered architectures and performance intensive, our commitment is to empower customers with the best class.”
These benefits aim to reduce complexity in data centers while allowing broader architectural flexibility.
Although technically promising, the real advantage of this integration will depend on the results of performance under work of production degree.
The collaboration of Xconn with Intel is also positioning itself as an important development, since according to the senior partner of Intel Ronak Singhal, the association will help to ensure that both the software and hardware components interact without problems, offering “end -to -end robust solutions.”
Companies expect this effort to promote an interoperable environment for PCIE and CXL technologies.
Even so, past experiences in the industry suggest that successful validation often takes time and more than one demonstration cycle.
The next demonstration will show a low latency and high bandwidth switching, highlighting the preparation of the infrastructure for applications such as training in AI/ML models, cloud computing and compound infrastructure.
According to reports, the XConn stand will have a completely based on standards configuration, but until the reference points are published, it is difficult to determine how much improvement users can expect compared to existing implementations of PCIE GEN 5.
Xconn has also associated with Scalefux to improve the interoperability CXL 3.1 for AI and cloud infrastructure.
While this indicates impulse, it does not confirm how well the solution is integrated with the types of work loads that today stress today’s architectures.
The implications for high -speed storage are significant if technology is delivered.
With the growing demand for the greatest SSD capabilities and faster SSD performance, PCIe Gen 6 could support faster data transfers between storage devices and processing units.
Even so, these theoretical gains should be tempered with skepticism until the field data confirms the impact.
The demonstration of Xconn can well mark the beginning of the next chapter in ai hardware. But for now, it is still a preview, not a test point.
Through techpowerup
