XCENA MX1 computational memory combines thousands of RISC-V nuclei with CXL 3.2 and Tiering SSD




  • Xcena introduced the mx1 computational memory with thousands of RISC-V nuclei in FMS 2025
  • MX1 offers a processing close to the data by reducing the CPU memory overload and enables the expansion supported by SSD at Petabyte scale
  • The product roadmap includes MX1P this year and MX1s in 2026 that supports CXL 3.2

In the recent FMS 2025 event (previously Flash Memory Summit but now called Future of Memory and Storage to better adapt to its expanded approach), the South Korean Startup Xcena removed the wraps of its first product, MX1 Memory.

MX1 is based on PCIE GEN6 and the Compute Express Link 3.2 standard. By calculating directly next to DRAM, the chip can reduce the overload of mobile data from one side between processors and memory.

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