- Qualcomm introduces High Bandwidth Compute (HBC) memory architecture
- It leverages a hybrid design that stacks LPDDR memory in a 3D space, leveraging multiple layers to essentially replace what the current generation of high-bandwidth memory (HBM4) does.
- The move, which makes use of Qualcomm’s extensive experience with LPDDR, is not only energy efficient but also offers massive amounts of bandwidth and up to 768GB of stacked memory for AI workloads.
Qualcomm is reviving its data center ambitions, leveraging its experience as a chip designer that excels in the low-power computing segment by focusing on an entirely new architecture: High Bandwidth Compute (HPC).
The solution is a hybrid version of existing LPDDR memory that Qualcomm has successfully stacked in 3D vertical space, not unlike the industry-standard high-bandwidth memory (HBM) and its latest version, HBM4, while offering significant power savings along the way.
The move is made possible by Qualcomm offering a near-memory computing architecture that combines memory with a compute-based die, with the former stacked vertically on top of the latter, effectively enabling up to 133TB/s.
An AI memory offer for the future?
While the current industry standard, HBM4, is already widely used, Qualcomm’s promised offering is expected to appear in mid-2027 as part of its next-generation AI inference accelerator, the AI250.
HBC Gen 1 offers a theoretical capacity of 768 GB that HBM4 struggles to match, and the 133 TB/s bandwidth advertised by Qualcomm is an achievement, given that modern HBM4 solutions offer approximately 3.3 TB/s per stack at the high end.
Some of these claims about bandwidth, however, might be a bit of an unfair comparison, as while HBM4 offers raw bandwidth, Qualcomm’s solution (and its theoretical speeds) is arguably in play only because it does much of the computing on-chip, which in some respects is an apples-to-oranges comparison.
Qualcomm, however, scores major wins with an AI industry increasingly obsessed with the power, or rather, lack thereof, to continue with many of its planned expansions by touting its efficiency gains where it claims between 6x bandwidth per watt versus HBM for larger batch sizes and efficiency gains of up to 200x when it comes to a mix of small and large inference batches, such as coding assistants.
Qualcomm’s list of partners includes Meta and Microsoft, and the former’s multi-generational agreement to use Qualcomm processors for AI stands out as a major win. Microsoft CEO Satya Nadela reassured investors by detailing the software giant’s partnership with the chip designer in the PC, local AI and data center segments.
As Microsoft increasingly seeks to address the environmental footprint of its AI data center deployment, and its CEO has already assured concerned parties and communities that the Redmond-based tech giant intends to be mindful of the water and energy footprints of currently planned and future data centers, this makes efficiency an even more important issue of late.
However, Qualcomm’s solution to “eliminate the HBM tax” does not exist in a vacuum; Competing solutions, such as High Bandwidth Flash, backed by Samsung, SanDisk, and SK Hynix, are also emerging as potential competitors that focus on a low-write, high-read situation that is typically the case for most AI inference workloads.
Perhaps most importantly, Qualcomm’s solution and the impressive numbers it delivers still lack independent, third-party test results that can verify its efficiency claims, even as Microsoft’s vote of confidence is seen as important for one of the biggest players in the mobile SoC business as it prepares to take a share of a growing but increasingly competitive data center pie in the coming decade.
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